In modern computer design, several communication channels provided in a computer system may be controlled by a single multi-channel controller, e.g. a DMA controller. When data are present on a channel, a CPU interrupt request may be generated to interrupt the CPU of the system for processing of the data. Various types of interrupt requests are possible. For example, when data are received by a communication channel one type of interrupt request may be asserted. However, when data are transmitted via a communication channel, a different type of interrupt request may be asserted.
When there are data present on multiple channels at the same time, multiple CPU interrupt requests may exist. These interrupt requests can be for the same or different types of interrupt requests. Typically, each one of several different interrupt flags is available to represent one of the several various types of interrupt requests that may be asserted.
Interrupt flags are used to indicate to the CPU that an interrupt request is being asserted. When there are various interrupt flags asserted, the CPU proceeds to service the various interrupt requests, indicated by the asserted interrupt flags, according to its own priority scheme.
Since there is only one available interrupt flag for any particular type of interrupt request, to indicate to the CPU that a request of the indicated type exists, it may be necessary to share access to the interrupt flag among several channels. Whenever a particular type of interrupt request is being asserted by more than one channel at the same time, a scheme for arbitrating access to the shared resource, e.g. a common interrupt flag, must be implemented.
When a single resource such as an interrupt flag is shared among several communication channels, fairness becomes important. Fairness involves the fair allocation of access to the resource so that no single channel dominates the use of the resource to the extent that other communication channels are unable to receive adequate access.
To insure that adequate access to the common interrupt flag is provided, interrupt select mechanisms are used to implement an arbitration scheme to allocate access to the interrupt flag in a fair manner. In this way, multiple requests for an interrupt among several channels are resolved in a manner that prevents any channel from locking out another channel completely. This insures that the CPU will service the interrupt requests of any particular type in the order they are assigned access to the interrupt flag by the interrupt select mechanism.
In one scheme for an interrupt select mechanism, a round robin scheme for sharing access to an interrupt flag fairly between multiple channels of equal priority is implemented.
In a known method of implementing an interrupt select mechanism using a round robin arbitration scheme, a state machine/counter, which will be referred to as a scanner, is driven by a multi-channel controller, e.g. a DMA controller. The scanner sequences through the channels checking for interrupt requests. The first channel the scanner comes across with an interrupt request pending locks the scanner on the channel and causes an interrupt flag to be set. The scanner remains locked on the channel until the interrupt request is cleared and the interrupt flag is reset. Thus, in the known system, when multiple interrupt flags are available for allocation, a separate scanner is needed for each interrupt type which is represented by an interrupt flag.
In the known system, once the interrupt is cleared, the scanner then proceeds to the next channel and sequences through all the other channels giving them a chance to generate an interrupt request and set the interrupt flag before allowing the initial channel to interrupt again. For each interrupt flag being used, representing a different type of interrupt request, a separate scanner plus interrupt select, set and clear logic in addition to other logic, is required.
Thus, the known system, which requires a scanner, select, set and clear logic for each interrupt flag available for allocation, becomes costly and inefficient to implement when there are multiple interrupt flags in a computer system.